The present invention relates generally to the field of electronic error detection; more particularly, to detecting errors in systems that transfer data and information between agents coupled to a bus, data link, or other type of input/output (I/O) interconnect.
Manufacturers of semiconductor devices face constant pressure to reduce the number of interconnects, especially in chipset platforms comprising multiple semiconductor devices interconnected on a common printed circuit board. Since the number of pins is a major factor in the costs of inter-chip connections, it is desirable to make such interconnects fast and narrow. This has led to the development of devices having fewer pins, and pins that can transmit signals very quickly.
One proposal addressing this problem is to utilize a half-duplex bus with distributed arbitration for I/O interconnects designed to connect I/O hubs and peripheral component interface (PCI) bridges (e.g., south bridges) to the memory hub controller (e.g., north bridge). It is well known that in a full-duplex bus, traffic can flow bi-directionally, simultaneously across separate sets of wires. A half-duplex bus is one in which there is a single lane of traffic (i.e., one set of wires) that is shared according to some sort of time-multiplexing scheme.
A common method to achieve synchronization on a half-duplex bus is via a global clock, also frequently referred to as a common or base clock. Each agent coupled to the bus usually has its own associated request signal line (REQ) used to gain ownership of the bus. In the case of synchronization via a global clock, each agent executes the same arbitration algorithm; asserting its request signal to convey its request to a remote agent; sampling the request signal driven by the remote agent; and then choosing which agent to grant ownership to based on the local and remote requests.
In one proposed design an additional control signal is employed for flow control (i.e., a STOP signal), and an additional signal for insuring data integrity (i.e., a PARITY signal). The STOP signal is asserted by the receiving agent to throttle the transmitting agent in cases, for example, such as buffer overflow at the receiving end. The PARITY signal encodes parity for detection of errors in the data signals.
Parity encoding is a well-known technique used to allow a receiving agent to detect an error in the received data. However, parity encoding is limited in detecting mis-synchronization of the agents due to errors in the control signals (e.g., REQ and STOP). This can lead, for instance, to misinterpretation of data as header information, or header information as data. In the situation where data is erroneously interpreted as header information, incorrect data can be written to a wrong address. One example of such a scenario is the STOP signal asserted by the receiving agent going undetected by the transmitting agent, possibly due to a faulty pin, or an intermittent break in the connector. Thus, corruption of the data files can occur before the inconsistency resulting from the original error is detected.
Therefore, what is needed is an error detection scheme for I/O interconnects that can detect mis-synchronization between agents despite possible failures in the control signals.
The present invention is a method of detecting synchronization errors during the transfer of data across a bus connected to transmitting and receiving agents. In one embodiment, the method comprises sending a first informational element from the transmitting agent to the receiving agent along with first parity signals encoded using a corresponding parity function. The receiving agent then receives the first informational element. The transmitting and receiving agents normally operate synchronously via control signals such that the receiving agent decodes the first parity signals using the corresponding parity function. A synchronization error condition is detected when the receiving agent decodes the first parity signals using a non-corresponding parity function.